ATMEGA128L-8MC View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATMEGA128L-8MC' PDF : 395 Pages View PDF
ATmega128
be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to
re-enable SPI Master mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero,
SCK is low when idle. Refer to Figure 77 and Figure 78 for an example. The CPOL func-
tionality is summarized below:
Table 70. CPOL functionality
CPOL
Leading edge
0
Rising
1
Falling
Trailing edge
Falling
Rising
• Bit 2 – CPHA: Clock Phase
The settings of the clock phase bit (CPHA) determine if data is sampled on the leading
(first) or trailing (last) edge of SCK. Refer to Figure 77 and Figure 78 for an example.
The CPHA functionality is summarized below:
Table 71. CPHA functionality
CPHA
Leading edge
0
Sample
1
Setup
Trailing edge
Setup
Sample
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a master. SPR1 and
SPR0 have no effect on the slave. The relationship between SCK and the Oscillator
Clock frequency fosc is shown in the following table:
Table 72. Relationship Between SCK and the Oscillator Frequency
SPI2X
0
0
0
0
1
1
1
1
SPR1
0
0
1
1
0
0
1
1
SPR0
0
1
0
1
0
1
0
1
SCK Frequency
fosc /4
fosc /16
fosc /64
fosc /128
fosc /2
fosc /8
fosc /32
fosc /64
2467O–AVR–10/06
169
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