ATMEGA128L-8MC View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATMEGA128L-8MC' PDF : 395 Pages View PDF
ATmega128
Figure 79. USART Block Diagram
UBRR[H:L]
BAUD RATE GENERATOR
UDR (Transmit)
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER
UDR (Receive)
Clock Generator
OSC
SYNC LOGIC
PARITY
GENERATOR
CLOCK
RECOVERY
DATA
RECOVERY
PARITY
CHECKER
PIN
CONTROL
XCK
Transmitter
TX
CONTROL
PIN
CONTROL
TxD
Receiver
RX
CONTROL
PIN
CONTROL
RxD
UCSRA
UCSRB
UCSRC
Note: Refer to Figure 1 on page 2, Table 36 on page 77, and Table 39 on page 80 for USART
pin placement.
The dashed boxes in the block diagram separate the three main parts of the USART
(listed from the top): Clock Generator, Transmitter, and Receiver. Control registers are
shared by all units. The clock generation logic consists of synchronization logic for exter-
nal clock input used by synchronous slave operation, and the baud rate generator. The
XCK (Transfer Clock) pin is only used by Synchronous Transfer mode. The Transmitter
consists of a single write buffer, a serial Shift Register, parity generator and control logic
for handling different serial frame formats. The write buffer allows a continuous transfer
of data without any delay between frames. The Receiver is the most complex part of the
USART module due to its clock and data recovery units. The recovery units are used for
asynchronous data reception. In addition to the recovery units, the receiver includes a
parity checker, control logic, a Shift Register and a two level receive buffer (UDR). The
receiver supports the same frame formats as the Transmitter, and can detect frame
error, data overrun and parity errors.
2467O–AVR–10/06
173
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