ATMEGA128L-8MC View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATMEGA128L-8MC' PDF : 395 Pages View PDF
receiver will in this case only use half the number of samples (reduced from 16 to 8) for
data sampling and clock recovery, and therefore a more accurate baud rate setting and
system clock are required when this mode is used. For the Transmitter, there are no
downsides.
External Clock
External clocking is used by the synchronous slave modes of operation. The description
in this section refers to Figure 80 for details.
External clock input from the XCK pin is sampled by a synchronization register to mini-
mize the chance of meta-stability. The output from the synchronization register must
then pass through an edge detector before it can be used by the transmitter and
receiver. This process introduces a two CPU clock period delay and therefore the maxi-
mum external XCK clock frequency is limited by the following equation:
fXCK
<
-f-O----S---C--
4
Note that fosc depends on the stability of the system clock source. It is therefore recom-
mended to add some margin to avoid possible loss of data due to frequency variations.
Synchronous Clock Operation
When Synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock
input (slave) or clock output (master). The dependency between the clock edges and
data sampling or data change is the same. The basic principle is that data input (on
RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is
changed.
Figure 81. Synchronous Mode XCK Timing.
UCPOL = 1 XCK
RxD / TxD
UCPOL = 0 XCK
Sample
RxD / TxD
Sample
The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and
which is used for data change. As Figure 81 shows, when UCPOL is zero the data will
be changed at rising XCK edge and sampled at falling XCK edge. If UCPOL is set, the
data will be changed at falling XCK edge and sampled at rising XCK edge.
176 ATmega128
2467O–AVR–10/06
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