ATMEGA161-8PC View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
ATMEGA161-8PC
Atmel Corporation
'ATMEGA161-8PC' PDF : 159 Pages View PDF
ATmega161(L)
The output compare registers are 8-bit read/write registers. The Timer/Counter Output Compare Registers contains the
data to be continuously compared with the Timer/Counter. Actions on compare matches are specified in TCCR0 and
TCCR2. A compare match does only occur if the Timer/Counter counts to the OCR value. A software write that sets
Timer/Counter and Output Compare Register to the same value does not generate a compare match.
A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event.
Timer/Counter 0 and 2 in PWM Mode
When PWM mode is selected, the Timer/Counter either wraps (overflows) when it reaches $FF or it acts as an up/down
counter.
If the up/down mode is selected, the Timer/Counter and the Output Compare Registers – OCR0 or OCR2 form an 8-bit,
free-running, glitch-free and phase correct PWM with outputs on the PB0(OC0/PWM0) or PB1(OC2/PWM2) pin.
If the overflow mode is selected, the Timer/Counter and the Output Compare Registers – OCR0 or OCR2 form an 8-bit,
free-running and glitch-free PWM, operating with twice the speed of the up/down counting mode.
PWM Modes (Up/Down and Overflow)
The two different PWM modes are selected by the CTC0 or CTC2 bit in the Timer/Counter Control Registers – TCCR0 or
TCCR2 respectively.
If CTC0/CTC2 is cleared and PWM mode is selected, the Timer/Counter acts as an up/down counter, counting up from $00
to $FF, where it turns and counts down again to zero before the cycle is repeated. When the counter value matches the
contents of the Output Compare Register, the PB0(OC0/PWM0) or PB1(OC2/PWM2) pin is set or cleared according to the
settings of the COMn1/COMn0 bits in the Timer/Counter Control Registers TCCR0 or TCCR2.
If CTC0/CTC2 is set and PWM mode is selected, the Timer/Counters will wrap and start counting from $00 after reaching
$FF. The PB0(OC0/PWM0) or PB1(OC2/PWM2) pin will be set or cleared according to the settings of COMn1/COMn0 on
a Timer/Counter overflow or when the counter value matches the contents of the Output Compare Register. Refer to Table
12 for details.
Table 12. Compare Mode Select in PWM Mode
CTCn COMn1 COMn0 Effect on Compare Pin
0
0
0
Not connected
0
0
1
Not connected
0
1
0
Cleared on compare match, up-counting. Set on compare match,
down-counting (non-inverted PWM).
0
1
1
Cleared on compare match, down-counting. Set on compare match,
up-counting (inverted PWM).
1
0
0
Not connected
1
0
1
Not connected
1
1
0
Cleared on compare match, set on overflow.
1
1
1
Set on compare match, cleared on overflow.
Note: n = 0 or 2
Frequency
fTCK0/2/510
fTCK0/2/510
fTCK0/2/256
fTCK0/2/256
Note that in PWM mode, the value to be written to the Output Compare Register is first transferred to a temporary location,
and then latched into the OCR when the Timer/Counter reaches $FF. This prevents the occurrence of odd-length PWM
pulses (glitches) in the event of an unsynchronized OCR0 or OCR2 write. See Figure 34 and Figure 35 for examples.
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