ATMEGA161-8PC View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
ATMEGA161-8PC
Atmel Corporation
'ATMEGA161-8PC' PDF : 159 Pages View PDF
ATmega161(L)
• Bit 1 - TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is
enabled. The corresponding interrupt (at vector $016) is executed if an overflow in Timer/Counter0 occurs, i.e., when the
TOV0 bit is set in the Timer/Counter Interrupt Flag Register – TIFR.
• Bit 0 - OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable
When the OCIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match inter-
rupt is enabled. The corresponding interrupt (at vector $014) is executed if a Compare0 match in Timer/Counter0 occurs,
i.e., when the OCF0 bit is set in the Timer/Counter Interrupt Flag Register – TIFR.
Timer/Counter Interrupt Flag Register – TIFR
Bit
$38 ($58)
Read/Write
Initial value
7
TOV1
R/W
0
6
OCF1A
R/W
0
5
OCIFB
R/W
0
4
TOV2
R/W
0
3
ICF1
R/W
0
2
OCF2
R/W
0
1
TOV0
R/W
0
0
OCF0
R/W
0
TIFR
• Bit 7 - TOV1: Timer/Counter1 Overflow Flag
The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in
SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow
Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000.
• Bit 6 - OCF1A: Output Compare Flag 1A
The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A – Output
Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-
tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare
match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed.
• Bit 5 - OCF1B: Output Compare Flag 1B
The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B – Output
Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-
tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare
match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed.
• Bit 4 - TOV2: Timer/Counter2 Overflow Flag
The bit TOV2 is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG
I-bit, and TOIE2 (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow inter-
rupt is executed.
• Bit 3 - ICF1: - Input Capture Flag 1
The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the
input capture register – ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input
Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed.
• Bit 2 - OCF2: Output Compare Flag 2
The OCF2 bit is set (one) when compare match occurs between the Timer/Counter2 and the data in OCR2 – Output Com-
pare Register 2. OCF2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively,
OCF2 is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE2 (Timer/Counter2 Compare match
InterruptA Enable), and the OCF2 are set (one), the Timer/Counter2 Compare match Interrupt is executed.
• Bit 1 - TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG
I-bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow
interrupt is executed.
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