ATMEGA161-8PC View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
ATMEGA161-8PC
Atmel Corporation
'ATMEGA161-8PC' PDF : 159 Pages View PDF
ATmega161(L)
Table 9. Compare Mode Select
COMn1
COMn0
Description
0
0
Timer/Counter disconnected from output pin OCn
0
1
Toggle the OCn output line.
1
0
Clear the OCn output line (to zero).
Notes:
1
1
Set the OCn output line (to one).
1. In PWM mode, these bits have a different function. Refer to Table 12 for a detailed description.
2. n = 0 or 2
• Bit 3 - CTC0/CTC2: Clear Timer/Counter on Compare Match
When the CTC0 or CTC2 control bit is set (one), Timer/Counter0 or Timer/Counter2 is reset to $00 in the CPU clock cycle
after a compare match. If the control bit is cleared, Timer/Counter continues counting and is unaffected by a compare
match. When a prescaling of 1 is used, and the compare register is set to C, the timer will count as follows if CTC0/CTC2 is
set:
... | C-1 | C | 0 | 1 | ...
When the prescaler is set to divide by 8, the timer will count like this:
... | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, C, C, C, C, C, C, C | 0, 0, 0, 0, 0, 0, 0, 0 | 1, 1, 1, ...
In PWM mode, this bit has a different function. If the CTC0 or CTC2 bit is cleared in PWM mode, the Timer/Counter acts as
an up/down counter. If the CTC0 or CTC2 bit is set (one), the Timer/Counter wraps when it reaches $FF. Refer to page 41
for a detailed description.
• Bits 2,1,0 - CS02, CS01, CS00/ CS22, CS21, CS20: Clock Select bits 2,1 and 0
The Clock Select bits 2,1 and 0 define the prescaling source of Timer/Counter0 and Timer/Counter2.
Table 10. Clock 0 Prescale Select
CS02
CS01
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
CS00
0
1
0
1
0
1
0
1
Description
Stop, the Timer/Counter0 is stopped.
CK
CK/8
CK/64
CK/256
CK/1024
External Pin PB0(T0), falling edge
External Pin PB0(T0), rising edge
39
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