ATMEGA261 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATMEGA261' PDF : 226 Pages View PDF
7.1.5
Internal PLL for Fast Peripheral Clock Generation - clkPCK
The internal PLL in ATtiny261/461/861 generates a clock frequency that is 8x multiplied from a
source input. By default, the PLL uses the output of the internal 8.0 MHz RC oscillator as source.
Alternatively, if the LSM bit of the PLLCSR is set the PLL will use the output of the RC oscillator
divided by two. Thus the output of the PLL, the fast peripheral clock is 64 MHz. The fast periph-
eral clock, or a clock prescaled from that, can be selected as the clock source for
Timer/Counter1or as a system clock. See Figure 7-2. The frequency of the fast peripheral clock
is divided by two when LSM of PLLCSR is set, resulting in a clock frequency of 32 MHz. Note,
that LSM can not be set if PLLCLK is used as a system clock.
Figure 7-2. PCK Clocking System
OSCCAL
LSM
PLLE
CKSEL3:0
CLKPS3:0
8.0 MHz
OSCILLATOR
XTAL1
XTAL2
OSCILLATORS
1/2
4 MHz
8 MHz
LOCK
DETECTOR
PLL
8x
1/4
64 / 32 MHz
16 MHz
8 MHz
PLOCK
PCK
PRESCALER
SYSTEM
CLOCK
The PLL is locked on the RC oscillator and adjusting the RC oscillator via OSCCAL register will
adjust the fast peripheral clock at the same time. However, even if the RC oscillator is taken to a
higher frequency than 8 MHz, the fast peripheral clock frequency saturates at 85 MHz (worst
case) and remains oscillating at the maximum frequency. It should be noted that the PLL in this
case is not locked any longer with the RC oscillator clock. Therefore, it is recommended not to
take the OSCCAL adjustments to a higher frequency than 8 MHz in order to keep the PLL in the
correct operating range.
The internal PLL is enabled when:
• The PLLE bit of the PLLCSR register is set.
• The CKSEL fuse are programmed to ‘0001’.
The PLLCSR bit PLOCK is set when PLL is locked.
Both internal RC oscillator and PLL are switched off in power down and stand-by sleep modes.
26 ATtiny261/ATtiny461/ATtiny861
7753E–AVR–06/10
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