ATMEGA261 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATMEGA261' PDF : 226 Pages View PDF
Figure 7-3. External Clock Drive Configuration
EXTERNAL
CLOCK
SIGNAL
CLKI
GND
When this clock source is selected, start-up times are determined by the SUT Fuses as shown in
Table 7-3.
Table 7-3.
SUT1..0
00
01
10
11
Start-up Times for the External Clock Selection
Start-up Time from
Power-down and Power-save
Additional Delay from
Reset
6 CK
14CK
6 CK
14CK + 4 ms
6 CK
14CK + 64 ms
Reserved
Recommended Usage
BOD enabled
Fast rising power
Slowly rising power
Note that the System Clock Prescaler can be used to implement run-time changes of the internal
clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page
32 for details.
7.5 High Frequency PLL Clock - PLLCLK
There is an internal PLL that provides nominally 64 MHz clock rate locked to the RC Oscillator
for the use of the Peripheral Timer/Counter1 and for the system clock source. When selected as
a system clock source, by programming the CKSEL fuses to ‘0001’, it is divided by four like
shown in Table 7-4. When this clock source is selected, start-up times are determined by the
SUT fuses as shown in Table 7-5. See also “PCK Clocking System” on page 26.
Table 7-4.
PLLCK Operating Modes
CKSEL3..0
0001
Nominal Frequency
16 MHz
Table 7-5.
SUT1..0
00
01
10
11
Start-up Times for the PLLCK
Start-up Time from Power
Down
14CK + 1K (1024) + 4 ms
Additional Delay from
Power-On-Reset (VCC = 5.0V)
4 ms
14CK + 16K (16384) + 4 ms
4 ms
14CK + 1K (1024) + 64 ms
4 ms
14CK + 16K (16384) + 64 ms
4 ms
Recommended usage
BOD enabled
Fast rising power
Slowly rising power
Slowly rising power
28 ATtiny261/ATtiny461/ATtiny861
7753E–AVR–06/10
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