ATtiny261/ATtiny461/ATtiny861
Figure 9-1. Reset Logic
DATA BUS
MCU Status
Register (MCUSR)
Power-on Reset
Circuit
BODLEVEL [1..0]
Pull-up Resistor
SPIKE
FILTER
Brown-out
Reset Circuit
9.0.3
Watchdog
Oscillator
Clock
CK
Generator
CKSEL[1:0]
SUT[1:0]
Delay Counters
TIMEOUT
Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level
is defined in “System and Reset Characteristics” on page 190. The POR is activated whenever
VCC is below the detection level. The POR circuit can be used to trigger the Start-up Reset, as
well as to detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the
Power-on Reset threshold voltage invokes the delay counter, which determines how long the
device is kept in RESET after VCC rise. The RESET signal is activated again, without any delay,
when VCC decreases below the detection level.
Figure 9-2. MCU Start-up, RESET Tied to VCC
VCCRR
VCC
VPORMAX
VPORMIN
RESET
TIME-OUT
V RST
t TOUT
INTERNAL
RESET
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