ATMEGA261 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATMEGA261' PDF : 226 Pages View PDF
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared
when INT1 is configured as a level interrupt.
• Bit 6 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set
(one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared
when INT0 is configured as a level interrupt.
• Bit 5 – PCIF: Pin Change Interrupt Flag
When a logic change on any PCINT15 pin triggers an interrupt request, PCIF becomes set
(one). If the I-bit in SREG and the PCIE bit in GIMSK are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it.
• Bits 4:0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny261/461/861 and will always read as zero.
11.1.4
PCMSK0 – Pin Change Mask Register A
Bit
0x23 (0x43)
Read/Write
Initial Value
7
PCINT7
R/W
1
6
PCINT6
R/W
1
5
PCINT5
R/W
0
4
PCINT4
R/w
0
3
PCINT3
R/W
1
2
PCINT2
R/W
0
1
PCINT1
R/W
0
0
PCINT0
R/W
0
PCMSK0
• Bits 7:0 – PCINT7:0: Pin Change Enable Mask 7..0
Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin.
If PCINT7:0 is set and the PCIE1 bit in GIMSK is set, pin change interrupt is enabled on the cor-
responding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is
disabled.
11.1.5
PCMSK1 – Pin Change Mask Register B
Bit
0x22 (0x42)
Read/Write
Initial Value
7
PCINT15
R/W
1
6
PCINT14
R/W
1
5
PCINT13
R/W
1
4
PCINT12
R/w
1
3
PCINT11
R/W
1
2
PCINT10
R/W
1
1
PCINT9
R/W
1
0
PCINT8
R/W
1
PCMSK1
• Bits 7:0 – PCINT15:8: Pin Change Enable Mask 15..8
Each PCINT15:8 bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT11:8 is set and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on
the corresponding I/O pin, and if PCINT15:12 is set and the PCIE1 bit in GIMSK is set, pin
change interrupt is enabled on the corresponding I/O pin. If PCINT15:8 is cleared, pin change
interrupt on the corresponding I/O pin is disabled.
54 ATtiny261/ATtiny461/ATtiny861
7753E–AVR–06/10
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