Table 12-5. Overriding Signals for Alternate Functions in PB3..PB0
Signal PB3/OC1B/
Name PCINT11
PB2/SCK/USCK/SCL/
OC1B/PCINT10
PB1/MISO/DO/OC1A/
PCINT9
PB0/MOSI/DI/SDA/
OC1A/PCINT8
PUOE 0
0
0
0
PUOV 0
0
0
0
DDOE 0
USI_TWO_WIRE • USIPOS 0
USI_TWO_WIRE •
USIPOS
DDOV 0
(USI_SCL_HOLD +
PORTB2) • DDB2 • USIPOS
0
(SDA + PORTB0) •
DDB0 • USIPOS
PVOE OC1B Enable
OC1B Enable + USIPOS •
USI_TWO_WIRE • DDB2
OC1A Enable +
OC1A Enable + USIPOS
• USI_THREE_WIRE
(USI_TWO_WIRE •
DDB0 • USIPOS)
PVOV OC1B
OC1B
OC1A + (DO • USIPOS) OC1A
PTOE 0
USITC • USIPOS
0
0
DIEOE
PCINT11 • PCIE
PCINT10 • PCIE + USISIE •
USIPOS
PCINT9 • PCIE
PCINT8 • PCIE +
(USISIE • USIPOS)
DIEOV 0
0
0
0
DI
PCINT11
USCK/SCL/PCINT10
PCINT9
DI/SDA/PCINT8
AIO
Note: 1. INTRC means that one of the internal RC Oscillators are selected (by the CKSEL fuses),
EXTCK means that external clock is selected (by the CKSEL fuses).
12.3.2
Alternate Functions of Port A
The Port A pins with alternate function are shown in Table 12-6.
Table 12-6. Port B Pins Alternate Functions
Port Pin
Alternate Function
PA7
ADC6 / AIN0 / PCINT7
PA6
ADC5 / AIN1 / PCINT6
PA5
ADC4 / AIN2 / PCINT5
PA4
ADC3 /ICP0/ PCINT4
PA3
AREF / PCINT3
PA2
ADC2 / INT1 / USCK / SCL / PCINT2
PA1
ADC1 / DO / PCINT1
PA0
ADC0 / DI / SDA / PCINT0
The alternate pin configuration is as follows:
• Port A, Bit 7- ADC6/AIN0/PCINT7
ADC6: Analog to Digital Converter, Channel 6.
AIN0: Analog Comparator Input. Configure the port pin as input with the internal pull-up switched
off to avoid the digital port function from interfering with the function of the Analog Comparator.
PCINT7: Pin Change Interrupt source 8.
66 ATtiny261/ATtiny461/ATtiny861
7753E–AVR–06/10