ATMEGA261 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATMEGA261' PDF : 226 Pages View PDF
ATtiny261/ATtiny461/ATtiny861
However, due to variation of the system clock frequency and duty cycle caused by Oscillator
source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum fre-
quency of an external clock source is less than fclk_I/O/2.5.
An external clock source can not be prescaled.
Figure 13-2. Prescaler for Timer/Counter0
clkI/O
Clear
PSR0
T0
Synchronization
clkT0
Note: 1. The synchronization logic on the input pins (T0) is shown in Figure 13-1.
13.1 Register Description
13.1.1
TCCR0B – Timer/Counter0 Control Register B
Bit
7
6
5
0x33 (0x53)
-
-
-
Read/Write
R
R
R
Initial Value
0
0
0
4
TSM
R/W
0
3
PSR0
R/W
0
2
CS02
R/W
0
1
CS01
R/W
0
0
CS01
R/W
0
TCCR0B
• Bit 4 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSR0 bit is kept, hence keeping the Prescaler Reset signal asserted.
This ensures that the Timer/Counter is halted and can be configured without the risk of advanc-
ing during configuration. When the TSM bit is written to zero, the PSR0 bit is cleared by
hardware, and the Timer/Counter start counting.
• Bit 3 – PSR0: Prescaler Reset Timer/Counter0
When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally cleared
immediately by hardware, except if the TSM bit is set.
• Bits 2, 1, 0 – CS02, CS01, CS00: Clock Select0, Bit 2, 1, and 0
The Clock Select0 bits 2, 1, and 0 define the prescaling source of Timer0.
71
7753E–AVR–06/10
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