ATXMEGA384D3-MH View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATXMEGA384D3-MH' PDF : 109 Pages View PDF
XMEGA D3
7.4.1
7.4.2
7.4.3
I/O Memory
All peripherals and modules are addressable through I/O memory locations in the data memory
space. All I/O memory locations can be accessed by the Load (LD/LDS/LDD) and Store
(ST/STS/STD) instructions, transferring data between the 32 general purpose registers in the
CPU and the I/O Memory.
The IN and OUT instructions can address I/O memory locations in the range 0x00 - 0x3F
directly.
I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and
CBI instructions. The value of single bits can be checked by using the SBIS and SBIC instruc-
tions on these registers.
The I/O memory address for all peripherals and modules in XMEGA D3 is shown in the ”Periph-
eral Module Address Map” on page 51.
SRAM Data Memory
The XMEGA D3 devices have internal SRAM memory for data storage.
EEPROM Data Memory
The XMEGA D3 devices have internal EEPROM memory for non-volatile data storage. It is
addressable either in a separate data space or it can be memory mapped into the normal data
memory space. The EEPROM memory supports both byte and page access.
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