AU80610006225AASLBXC View Datasheet(PDF) - Intel
Part Name
Description
MFG CO.
'AU80610006225AASLBXC' PDF : 80 Pages View PDF
Signal Description
2.6
LVDS Signals
Table 2-11.LVDS Signals
Signal Name
Description
Direction Type
LVD_A_DATAP[2:0]
LVD_A_DATAN[2:0]
LVD_A_CLKP
LVD_A_CLKN
LVD_IBG
LVD_VBG
LVD_VREFH
LVD_VREFL
LVDD_EN
LBKLT_EN
LBKLT_CTL
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
Differential data output - positive
Differential data output - negative
Differential clock output - positive
Differential clock output - negative
LVDS Reference Current. Need 2.37 kOhms
pull-down resistor
Reserved. No connect.
Reserved. Can be connected to VSS or left as
No Connect.
Reserved. Can be connected to VSS or left as
No Connect.
LVDS panel power enable: Panel power control
enable control.
This signal is also called VDD_DBL in the CPIS
specification and is used to control the VDC
source to the panel logic.
LVDS backlight enable: Panel backlight enable
control.
This signal is also called ENA_BL in the CPIS
specification and is used to gate power into the
backlight circuitry.
Note: The accuracy of the PWM duty cycle of
LBKLT_CTL signal for any given value will be
within ±20 ns.
Panel backlight brightness control: Panel
brightness control. This signal is also called
VARY_BL in the CPIS specification and is used
as the PWM clock input signal.
I2C based control signal (clock) for External
SSC clock chip control - optional
I2C based control signal (data) for External
SSC clock chip control - optional
Display Data Channel clock
Display Data Channel data
O
LVDS
O
LVDS
O
LVDS
O
LVDS
I/O
Ref
O
Analog
I
Ref
I
Ref
O
HVCMOS
O
HVCMOS
O
HVCMOS
I/O
COD
I/O
COD
I/O
COD
I/O
COD
Datasheet
23
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