AU80610006225AASLBXC View Datasheet(PDF) - Intel
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MFG CO.
'AU80610006225AASLBXC' PDF : 80 Pages View PDF
Low Power Features
The processor core implements two software interfaces for requesting low power
states: MWAIT instruction extensions with sub-state hints and P_LVLx reads to the
ACPI P_BLK register block mapped in the processor core’s I/O address space. The
P_LVLx I/O reads are converted to equivalent MWAIT C-state requests inside the
processor core and do not directly result in I/O reads on the processor core bus. The
monitor address does not need to be setup before using the P_LVLx I/O read interface.
The sub-state hints used for each P_LVLx read can be configured in a software
programmable MSR by BIOS.
Figure 6-3. Idle Power Management Breakdown of the Processor Cores
Thread 0 Thread 1
Thread 0 Thread 1
Core 0 State
Core 1 State
Processor Package State
Entry and exit of C-states at the thread and core level are show in the following figure.
Figure 6-4. Thread and Core C-state
C1
MWAIT
Core
state
break
MWAIT
(C1)
C0
HLT
instruction
HLT
break
C 1/Auto
Halt
NOTES:
1.
halt break = A20M# transition, INIT#, INTR, NMI, PREQ#, SMI# or APIC interrupt.
Datasheet
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