AV1889Y View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
'AV1889Y' PDF : 35 Pages View PDF
ICS1889
Extended Control Register (register 16)
BIT
Definition
When bit = 0
When bit = 1
15 Command Register Override Don’t allow write
Allow write
14 Reserved for ICS
Write logic zero. Read unspecified.
13 Reserved for ICS
Write logic zero. Read unspecified.
12 Reserved for ICS
Write logic zero. Read unspecified.
11 Reserved for ICS
Write logic zero. Read unspecified.
10 PHY address - S4
9 PHY address - S3
MII management
8 PHY address - S2
Register address code
7 PHY address - S1
0 - 31 Read Only
6 PHY address - S0
5 Reserved for ICS
Write logic zero. Read unspecified.
4 Far End Fault
Disabled
Enabled
3 Transmit Far End Fault
No fault transmitted
Fault transmitted
2 Invalid Error Code Test
Disabled
Enabled
1 Reserved for ICS
Write logic zero. Read unspecified.
0 Reserved for ICS
Write logic zero. Read unspecified.
Access
RW
RW/0
RW/0
RW/0
RW/0
CW
CW
CW
CW
CW
RW/0
RW
RW
RW
RW/0
RW/0
Default
0
—
—
—
—
P4RD
P3TD
P2LI
P1CL
P0FD
—
1
0
0
—
—
Extended Control Register (register 16)
The Extended Control Register is a 16-bit read write register
used to pre-program the ICS1889. At power-up and reset, this
register will be loaded to the default values specified. It may
subsequently be read or written. If written, the result is bit
dependent as discussed below.
Command Register Override (bit 15)
If set to a logic one, this bit allows a subsequent write to the
Status Register (register 1) and the PHY identifier registers 2
and 3. The contents of registers 2 and 3 may be set to any
value. The Status Register may have certain specified bits set
or reset. The first write to registers 1, 2 or 3 after this bit is set
will reset it preventing subsequent writes from having any
effect.
Reserved (bit 14)
This bit is reserved for ICS use. It must always be written with
a logic zero. The value of this bit when read is unspecified and
may be a logic zero or one.
Reserved (bit 13)
This bit is reserved for ICS use. It must always be written with
a logic zero. The value of this bit, when read, is unspecified
and may be a logic zero or one.
Reserved (bit 12)
This bit is reserved for ICS use. It must always be written with
a logic zero. The value of this bit when read is unspecified and
may be a logic zero or one.
Reserved (bit 11)
This bit is reserved for ICS use. It must always be written with
a logic zero. The value of this bit when read is unspecified and
may be a logic zero or one.
PHY Address (Bits 10 through 6)
These 5 bits are used to indicate the address of the ICS1889
on the management port of the MII (any number in the range
0 - 31). A read returns the address. Extra care should be taken
if a command override write is performed on these bits, as a
change in the PHY address must be accounted for by the
device reading and writing to the MII Management interface.
Reserved (bit 5)
This bit is reserved for ICS use. It must always be written with
a logic zero. The value of this bit when read is unspecified and
may be a logic zero or one.
14
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