C8051F040 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
'C8051F040' PDF : 328 Pages View PDF
C8051F040/1/2/3/4/5/6/7
SFR Definition 15.1. FLACL: Flash Access Limit
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
SFR Address: 0xB7
SFR Page: F
Bits 7-0: FLACL: Flash Access Limit.
This register holds the high byte of the 16-bit program memory read/write/erase limit
address. The entire 16-bit access limit address value is calculated as 0xNN00 where NN is
replaced by contents of FLACL. A write to this register sets the Flash Access Limit. This reg-
ister can only be written once after any reset. Any subsequent writes are ignored until the
next reset.
SFR Definition 15.2. FLSCL: Flash Memory Control
R/W
FOSE
Bit7
R/W
FRAE
Bit6
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Reserved Reserved Reserved Reserved Reserved FLWE 10000000
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
SFR Address: 0xB7
SFR Page: 0
Bit7:
Bit6:
Bits5-1:
Bit0:
FOSE: Flash One-Shot Timer Enable
This is the timer that turns off the sense amps after a Flash read.
0: Flash One-Shot Timer disabled.
1: Flash One-Shot Timer enabled (recommended setting).
FRAE: Flash Read Always Enable
0: Flash reads occur as necessary (recommended setting).
1: Flash reads occur every system clock cycle.
RESERVED. Read = 00000b. Must Write 00000b.
FLWE: Flash Write/Erase Enable
This bit must be set to allow Flash writes/erases from user software.
0: Flash writes/erases disabled.
1: Flash writes/erases enabled.
184
Rev. 1.5
Share Link: 
