C8051F061 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
'C8051F061' PDF : 328 Pages View PDF
C8051F060/1/2/3/4/5/6/7
Table 4.1. Pin Definitions (Continued)
Name
P5.2/A10
Pin Numbers
F060 F061 F064 F065
F062 F063 F066 F067
86
86
P5.3/A11 85
85
P5.4/A12 84
84
P5.5/A13 83
83
P5.6/A14 82
82
P5.7/A15 81
81
P6.0/A8m/ 80
80
A0
P6.1/A9m/ 79
79
A1
P6.2/A10m/ 78
78
A2
P6.3/A11m/ 77
77
A3
P6.4/A12m/ 76
76
A4
P6.5/A13m/ 75
75
A5
P6.6/A14m/ 74
74
A6
P6.7/A15m/ 73
73
A7
P7.0/AD0m/ 72
72
D0
P7.1/AD1m/ 71
71
D1
Type Description
D I/O Port 5.2. See Port Input/Output section for complete
description.
D I/O Port 5.3. See Port Input/Output section for complete
description.
D I/O Port 5.4. See Port Input/Output section for complete
description.
D I/O Port 5.5. See Port Input/Output section for complete
description.
D I/O Port 5.6. See Port Input/Output section for complete
description.
D I/O Port 5.7. See Port Input/Output section for complete
description.
D I/O
Port 6.0. See Port Input/Output section for complete
description.
Bit 8 External Memory Address Bus (Multiplexed
mode).
Bit 0 External Memory Address Bus (Non-multi-
plexed mode).
D I/O Port 6.1. See Port Input/Output section for complete
description.
D I/O Port 6.2. See Port Input/Output section for complete
description.
D I/O Port 6.3. See Port Input/Output section for complete
description.
D I/O Port 6.4. See Port Input/Output section for complete
description.
D I/O Port 6.5. See Port Input/Output section for complete
description.
D I/O Port 6.6. See Port Input/Output section for complete
description.
D I/O Port 6.7. See Port Input/Output section for complete
description.
D I/O
Port 7.0. See Port Input/Output section for complete
description.
Bit 0 External Memory Address/Data Bus (Multi-
plexed mode).
Bit 0 External Memory Data Bus (Non-multiplexed
mode).
D I/O Port 7.1. See Port Input/Output section for complete
description.
Rev. 1.2
43
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