C8051F061 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
'C8051F061' PDF : 328 Pages View PDF
C8051F060/1/2/3/4/5/6/7
5. 16-Bit ADCs (ADC0 and ADC1)
The ADC subsystem for the C8051F060/1/2/3/4/5/6/7 consists of two 1 Msps, 16-bit successive-approxi-
mation-register ADCs with integrated track-and-hold, a Programmable Window Detector, and a DMA inter-
face (see block diagrams in Figure 5.1 and Figure 5.2). The ADCs can be configured as two separate,
single-ended ADCs, or as a differential pair. The Data Conversion Modes, Window Detector, and DMA
interface are all configurable under software control via the Special Function Registers shown in Figure 5.1
and Figure 5.2. The voltage references used by ADC0 and ADC1 are selected as described in Section 5.2.
The ADCs and their respective track-and-hold circuitry can be independently enabled or disabled with the
Special Function Registers. Either ADC can be enabled by setting the ADnEN bit in the ADC’s Control reg-
ister (ADCnCN) to logic 1. The ADCs are in low power shutdown when these bits are logic 0.
AIN0
AIN0G
(DC, -0.2 to 0.6 V)
SYSCLK ÷
AV+
AD0EN
16-Bit
SAR
ADC0
ADC0 Data Bus
16
00
Start Conversion 01
10
11
AD0BUSY (W)
Timer 3 Overflow
CNVSTR0
Timer 2 Overflow
ADC0CF
ADC0CN
AV+
AD1EN
AIN1
AIN1G
(DC, -0.2 to 0.6 V)
SYSCLK ÷
16-Bit
SAR
ADC1
ADC1 Data Bus
16
000
Start Conversion 010
100
110
xx1
AD1BUSY (W)
Timer 3 Overflow
CNVSTR1
Timer 2 Overflow
AD0BUSY (W)
ADC1CF
ADC1CN
Figure 5.1. 16-Bit ADC0 and ADC1 Control Path Diagram
Rev. 1.2
51
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