C8051F064 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
'C8051F064' PDF : 328 Pages View PDF
C8051F060/1/2/3/4/5/6/7
6.2. DMA0 Instruction Format
DMA instructions can request single-ended data from both ADC0 and ADC1, as well as the differential
combination of the two ADC inputs. The instruction format is identical to the DMA0IDT register, shown in
Figure 6.7. Depending on which bits are set to ‘1’ in the instruction word, either 2 or 4 bytes of data will be
written to XRAM for each DMA instruction cycle (excluding End-Of-Operation instructions). Table 6.1
details all of the valid DMA instructions. Instructions not listed in the table are not valid DMA instructions,
and should not be used. Note that the ADCs can be independently controlled by the microcontroller when
their outputs are not requested by the DMA.
Table 6.1. DMA0 Instruction Set
Instruction
Word
Description
First Data Written
to XRAM (2 bytes)
Second Data
Written to XRAM
(2 bytes)
00000000b End-Of-Operation
none
none
10000000b End-Of-Operation with Continuous Conversion
none
none
x0010000b Retrieve ADC0 Data
ADC0H:ADC0L
none
x0100000b Retrieve ADC1 Data
ADC1H:ADC1L
none
x0110000b Retrieve ADC0 and ADC1 Data
ADC0H:ADC0L
ADC1H:ADC1L
x10x0000b Retrieve Differential Data
ADC0H:ADC0L
(differential result
from both ADCs)
none
x11x0000b Retrieve Differential and ADC1 Data
ADC0H:ADC0L
(differential result
from both ADCs)
ADC1H:ADC1L
6.3. XRAM Addressing and Setup
The DMA Interface can be configured to access either on-chip or off-chip XRAM. Any writes to on-chip
XRAM by the DMA Control Logic occur when the processor core is not accessing the on-chip XRAM. This
ensures that the DMA will not interfere with processor instruction timing.
Off-chip XRAM access (only available on the C8051F060/2/4/6) is controlled by the DMA0HLT bit in
DMA0CF (DMA Configuration Register, Figure 6.5). The DMA will have full access to off-chip XRAM when
this bit is ‘0’, and the processor core will have full access to off-chip XRAM when this bit is ‘1’. The
DMA0HLT bit should be controlled in software when both the processor core and the DMA Interface
require access to off-chip XRAM data space. Before setting DMA0HLT to ‘1’, the software should check the
DMA0XBY bit to ensure that the DMA is not currently accessing off-chip XRAM. The processor core can-
not access off-chip XRAM while DMA0HLT is ‘0’. The processor will continue as though it was able to per-
form the desired memory access, but the data will not be written to or read from off-chip XRAM. When the
processor core is finished accessing off-chip XRAM, DMA0HLT should be set back to ‘0’in software to
return control to the DMA Interface. The DMA Control Logic will wait until DMA0HLT is ‘0’ before writing
data to off-chip XRAM. If new data becomes available to the DMA Interface before the previous data has
been written, an overflow condition will occur, and the new data word may be lost.
The Data Address Pointer Registers (DMA0DSH and DMA0DSL) contain the 16-bit XRAM address loca-
tion where the DMA interface will write data. When the DMA is initially enabled, the DMA Data Address
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Rev. 1.2
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