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Table 6.5. Interrupt Summary
Interrupt Source
Interrupt
Vector
Priority
Order
Pending Flag
Enable
Flag
Priority
Control
Reset
External Interrupt 0
(/INT0)
0x0000
0x0003
Top None
0 IE0 (TCON.1)
N/A
N/A
Always
Enabled
Always
Highest
Y
Y
EX0 (IE.0)
PX0
(IP.0)
Timer 0 Overflow
0x000B
1 TF0 (TCON.5)
Y Y ET0 (IE.1) PT0 (IP.1)
External Interrupt 1
(/INT1)
Timer 1 Overflow
UART0
0x0013
0x001B
0x0023
2 IE1 (TCON.3)
3 TF1 (TCON.7)
4
RI0 (SCON0.0)
TI0 (SCON0.1)
Y
Y
EX1 (IE.2)
PX1
(IP.2)
Y Y ET1 (IE.3) PT1 (IP.3)
Y
N
ES0 (IE.4)
PS0
(IP.4)
USB0
VBUS Level
0x0043
0x007B
8 Special*
15 N/A
N
N
EUSB0
(EIE1.1)
N/A
N/A
EVBUS
(EIE2.0)
PUSB0
(EIP1.1)
PVBUS
(EIP2.0)
*Note: See Section “12.8. Interrupts” on page 101 for more details about the USB interrupt.
6.3.5. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the
data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt
conditions for the peripheral and the behavior of its interrupt-pending flag(s).
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