C8051F326/7
10.2. Internal Low-Frequency (L-F) Oscillator
C8051F326/7 devices include a low-frequency oscillator. The OSCLCN register (see SFR Definition 10.3)
is used to enabled the oscillator.
SFR Definition 10.3. OSCLCN: Internal L-F Oscillator Control
R/W
R
OSCLEN
—
Bit7
Bit6
R
R
R
R
R
R
Reset Value
—
—
—
—
—
—
0xxxxxxx
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xE3
Bit7:
Bit6–0:
OSCLEN: Internal L-F Oscillator Enable.
0: Internal L-F Oscillator Disabled.
1: Internal L-F Oscillator Enabled.
Unused. Read = 0000000b. Write = don’t care.
10.3. CMOS External Clock Input
A CMOS clock can be used as an external clock input. The CMOS clock should be wired to the XTAL2 pin
(P0.3) as shown in Figure 10.1 on Page 71. Port pins must be configured when using the external oscilla-
tor circuit. The Port I/O Crossbar should be configured to allow digital inputs be setting INPUTEN (GPI-
OCN.6). Also, P0.3 should be configured to open drain mode. See Section “11. Port Input/Output” on
page 79 for more information.
74
Rev. 1.1