C8051F327 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
'C8051F327' PDF : 141 Pages View PDF
C8051F326/7
11. Port Input/Output
On-Chip digital resources are available through 15 I/O pins. Port pins are organized as shown in
Figure 11.1. Each of the Port pins can be used as general-purpose I/O (GPIO). Some port pins can be
dedicated to special signals such as /SYSCLK, UART TX and RX, and XTAL2 external clock input.
All Port I/Os are 5 V tolerant (refer to Figure 11.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,2,3). Com-
plete Electrical Specifications for Port I/O are given in Table 11.1 on page 85.
/SYSCLK
P0.0
/INT0
P0.1
/INT0
P0.2
GPIOCN.0
(P0.0 - OUT)
MUX
I/O
Cell
(P0.0 - IN)
TMOD.3
I/O
Cell
TMOD.3
I/O
Cell
XTAL2
I/O
Cell
P0.3
P0.4
UART
P0.5
(P0.4 - IN)
I/O
(P0.4 - OUT)
Cell
(P0.5 - IN)
I/O
(P0.5 - OUT)
Cell
P0.6
2
P0.7
I/O
Cells
P2.0
6
P2.5
C2D
I/O
Cells
I/O
P3.0
Cell
Figure 11.1. Port I/O Functional Block Diagram
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.5
P3.0
Rev. 1.1
79
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