C8051F352 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F352

8 k ISP Flash MCU Family

Silicon Laboratories 

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C8051F350/1/2/3

SFR Definition 7.1. REF0CN: Reference Control

R

R

R

R

R

R

R/W

R/W

Reset Value

—

—

—

—

—

—

BIASE REFBE 00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0xD1

NOTE: Modification of this register is not necessary in most applications. The appropriate circuitry is

enabled when it is needed by a peripheral.

Bits7–2:

Bit1:

Bit0:

Unused. Read = 000000b; Write = don’t care.

BIASE: Internal Oscillator Bias Enable.

This bit is ORed with the Internal Oscillator Enable bit to enable the internal oscillator bias

generator.

0: Internal Oscillator Bias enable determined by Internal Oscillator Enable bit.

1: Internal Oscillator Bias Generator On.

REFBE: Internal Reference Bias Enable Bit.

This bit is ORed with the Enable bits for ADC0, IDAC0, IDAC1, and the Clock Multiplier to

enable the internal bandgap generator.

0: Internal Reference Bias enable determined by individual component.

1: Internal Reference Bias enabled.

74

Rev. 1.1

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