C8051F362-GM2 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
'C8051F362-GM2' PDF : 288 Pages View PDF
C8051F360/1/2/3/4/5/6/7/8/9
SFR Definition 9.8. PSW: Program Status Word
SFR Page: all pages
SFR Address: 0xD0
R/W
R/W
CY
AC
Bit7
Bit6
(bit addressable)
R/W
R/W
R/W
R/W
F0
RS1
RS0
OV
Bit5
Bit4
Bit3
Bit2
R/W
R
Reset Value
F1
PARITY 00000000
Bit1
Bit0
Bit 7: CY: Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow
(subtraction). It is cleared to 0 by all other arithmetic operations.
Bit 6: AC: Auxiliary Carry Flag
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow
from (subtraction) the high order nibble. It is cleared to 0 by all other arithmetic operations.
Bit 5: F0: User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.
Bits 4–3: RS1–RS0: Register Bank Select.
These bits select which register bank is used during register accesses.
Bit 2:
Bit 1:
Bit 0:
RS1
RS0 Register Bank Address
0
0
0
0x00–0x07
0
1
1
0x08–0x0F
1
0
2
0x10–0x17
1
1
3
0x18–0x1F
OV: Overflow Flag.
This bit is set to 1 under the following circumstances:
• An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
• A MUL instruction results in an overflow (result is greater than 255).
• A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other
cases.
F1: User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
PARITY: Parity Flag.
This bit is set to 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum
is even.
Rev. 1.0
103
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