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C8051F367-GM2 View Datasheet(PDF) - Silicon Laboratories

Part Name
Description
MFG CO.
C8051F367-GM2
Silabs
Silicon Laboratories Silabs
'C8051F367-GM2' PDF : 288 Pages View PDF
C8051F360/1/2/3/4/5/6/7/8/9
12.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until VDD settles above
VRST. A delay occurs before the device is released from reset; the delay decreases as the VDD ramp time
increases (VDD ramp time is defined as how fast VDD ramps from 0 V to VRST). Figure 12.2. plots the
power-on and VDD Monitor reset timing. For ramp times less than 1 ms, the power-on reset delay (TPORDe-
lay) is typically less than 0.3 ms.
Note: The maximum VDD ramp time is 1 ms; slower ramp times may cause the device to be released from
reset before VDD reaches the VRST level.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic ‘1’. When PORSF
is set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data mem-
ory should be assumed to be undefined after a power-on reset. The VDD Monitor is enabled following a
power-on reset.
VDD
2.70
2.55
VRST
2.0
1.0
t
Logic HIGH /RST
Logic LOW
TPORDelay
Power-On
Reset
VDD
Monitor
Reset
Figure 12.2. Power-On and VDD Monitor Reset Timing
Rev. 1.0
129
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