C8051F367-GM2 View Datasheet(PDF) - Silicon Laboratories
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MFG CO.
'C8051F367-GM2' PDF : 288 Pages View PDF
C8051F360/1/2/3/4/5/6/7/8/9
12.2. Power-Fail Reset/VDD Monitor
When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 12.2). When VDD returns
to a level above VRST, the CIP-51 will be released from the reset state. Note that even though internal data
memory contents are not altered by the power-fail reset, it is impossible to determine if VDD dropped below
the level required for data retention. If the PORSF flag reads ‘1’, the data may no longer be valid. The VDD
Monitor is enabled after power-on resets; however its defined state (enabled/disabled) is not altered by any
other reset source. For example, if the VDD Monitor is disabled and a software reset is performed, the VDD
Monitor will still be disabled after the reset. To protect the integrity of Flash contents, the VDD Monitor
must be enabled and selected as a reset source if software contains routines which erase or write
Flash memory. If the VDD Monitor is not enabled, any erase or write performed on Flash memory
will cause a Flash Error device reset.
The VDD Monitor must be enabled before it is selected as a reset source. Selecting the VDD Monitor
as a reset source before it is enabled and stabilized may cause a system reset. The procedure for config-
uring the VDD Monitor as a reset source is shown below:
Step 1. Enable the VDD Monitor (VDMEN bit in VDM0CN = ‘1’).
Step 2. Wait for the VDD Monitor to stabilize (approximately 5 µs).
Note: This delay should be omitted if software contains routines which erase or
write Flash memory.
Step 3. Select the VDD Monitor as a reset source (PORSF bit in RSTSRC = ‘1’).
See Table 12.1 for complete electrical characteristics of the VDD Monitor.
Note: Software should take care not to inadvertently disable the VDD Monitor as a reset source
when writing to RSTSRC to enable other reset sources or to trigger a software reset. All writes to
RSTSRC should explicitly set PORSF to '1' to keep the VDD Monitor enabled as a reset source.
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Rev. 1.0
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