C8051F901-GD View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
C8051F901-GD
Silicon Laboratories
'C8051F901-GD' PDF : 318 Pages View PDF
C8051F91x-C8051F90x
5. SAR ADC with 16-bit Auto-Averaging Accumulator and
Autonomous Low Power Burst Mode
The ADC0 on C8051F91x-C8051F90x devices is a 300 ksps, 10-bit or 75 ksps, 12-bit (‘F912/02 only)
successive-approximation-register (SAR) ADC with integrated track-and-hold and programmable window
detector. ADC0 also has an autonomous low power Burst Mode which can automatically enable ADC0,
capture and accumulate samples, then place ADC0 in a low power shutdown mode without CPU
intervention. It also has a 16-bit accumulator that can automatically oversample and average the ADC
results. See Section 5.4 for more details on using the ADC in 12-bit mode.
The ADC is fully configurable under software control via Special Function Registers. The ADC0 operates in
Single-ended mode and may be configured to measure various different signals using the analog
multiplexer described in “5.7. ADC0 Analog Multiplexer” on page 78. The voltage reference for the ADC is
selected as described in “5.9. Voltage and Ground Reference Options” on page 83.
ADC0CN
ADC0TK
ADC0PWR
Burst Mode Logic
VDD
From
AMUX0
AIN+
10/12-Bit
SAR
ADC
000
Start
Conversion 001
010
011
100
AD0BUSY (W)
Timer 0 Overflow
Timer 2 Overflow
Timer 3 Overflow
CNVSTR Input
16-Bit Accumulator
ADC0LTH ADC0LTL
AD0WINT
W indow
Compare
32
Logic
ADC0CF
ADC0GTH ADC0GTL
Figure 5.1. ADC0 Functional Block Diagram
Rev. 1.0
61
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