C8051F97X View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
'C8051F97X' PDF : 455 Pages View PDF
17.1. ADC0 Analog Multiplexer
The ADC0 module has an analog multiplexer that selects the positive inputs to the single-ended ADC0. Any of the
following may be selected as the positive input: pins from the analog pad selector (AMUX0), the on-chip
temperature sensor, internal regulated digital supply voltage (output of VREG0), VDD, or GND. The ADC0 input
channels are selected in the ADC0MX register. If any of the internal signals are selected as the ADC0 input
channel, the AMUX0 registers must not select an external pin and all be cleared to 0.
Important Note: Only one AMUX0 input should be enabled at a time when using ADC0 with AMUX0 (ADC0MX =
0).
Table 17.1. ADC0 Input Multiplexer Channels
ADC0MX setting
00000
00001 – 11010
11011
11100
11101
11110
11111
Signal Name
ADC0.0
Reserved
TEMP
VDD
LDO
Reserved
GND
QFN-48 Pin Name QFN-32 Pin Name QFN-24 Pin Name
AMUX Input Selector
Reserved
Temperature Sensor Output
VDD Supply Voltage
Internal LDO regulator output
Reserved
Ground
Important Note about ADC0 Input Configuration: A port pin selected as ADC0 input should be configured as
follows:
1. Set to analog mode input by clearing to 0 the corresponding bit in register PnMDIN.
2. Force the Priority Crossbar Decoder to skip the pin by setting 1 to the corresponding bit in register PnSKIP.
3. Disable the auto-ground for the pin by setting 1 to the corresponding bit in the port latch (Pn).
4. Enable the analog pad selection for the pin by setting 1 to the corresponding bit in the AMUX0Pn register.
See “26. Port I/O (Port 0, Port 1, Port 2, Port 3, Port 4, Port 5, Port 6, Crossbar, and Port Match)” on page 277 for
more Port I/O configuration details.
105
Rev 1.1
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