C8051T603 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
'C8051T603' PDF : 168 Pages View PDF
C8051T600/1/2/3/4/5/6
Port
P0
In this example, the crossbar is configured to
Pin 0 1 2 3 4 5 6 7 assign the UART TX0 and RX0 signals, the
SMBus signals, and the SYSCLK signal. Note
Special
that the SMBus signals are assigned as a pair,
Function
and there are no pins skipped using the XBR0
Signals
register.
TX0
These boxes represent the port pins which
RX0
are used by the peripherals in this configuration.
SDA
SCL
CP0
CP0A
SYSCLK
1st TX0 is assigned to P0.4
2nd RX0 is assigned to P0.5
3rd SDA and SCL are assigned to P0.0 and P0.1,
respectively.
4th SYSCLK is assigned to P0.2
CEX0
CEX1
CEX2
All unassigned pins can be used as GPIO or for
other non-crossbar functions.
ECI
T0
T1
Pin Skip 0 0 0 0 0 0 0 x
Settings
XBR0
Figure 22.4. Priority Crossbar Decoder Example 1 - No Skipped Pins
112
Rev. 1.2
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