C8051T603 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
'C8051T603' PDF : 168 Pages View PDF
C8051T600/1/2/3/4/5/6
Port
P0
In this example, the crossbar is configured to
Pin 0 1 2 3 4 5 6 7 assign the UART TX0 and RX0 signals, the
SMBus signals, and the SYSCLK signal. Note
Special
that the SMBus signals are assigned as a pair.
Function
Additionally, pins P0.0 and P0.3 are configured
Signals
to be skipped using the XBR0 register.
TX0
These boxes represent the port pins which
RX0
are used by the peripherals in this configuration.
SDA
SCL
CP0
CP0A
SYSCLK
1st TX0 is assigned to P0.4
2nd RX0 is assigned to P0.5
3rd SDA and SCL are assigned to P0.2 and P0.3,
respectively.
4th SYSCLK is assigned to P0.6
CEX0
CEX1
CEX2
All unassigned pins, including those skipped by
XBR0 can be used as GPIO or for other non-
crossbar functions.
ECI
T0
T1
Pin Skip 1 0 0 1 0 0 0 x
Settings
XBR0
Figure 22.5. Priority Crossbar Decoder Example 2 - Skipping Pins
Registers XBR1 and XBR2 are used to assign the digital I/O resources to the physical I/O Port pins. Note
that when the SMBus is selected, the crossbar assigns both pins associated with the SMBus (SDA and
SCL). UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to P0.4;
UART RX0 is always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized func-
tions have been assigned.
Rev. 1.2
113
Share Link: 
