C8051T603 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
'C8051T603' PDF : 168 Pages View PDF
C8051T600/1/2/3/4/5/6
15. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types.
15.1. Program Memory
The CIP-51 core has a 64 kB program memory space. The C8051T600/1 implements 8192 bytes of this
program memory space as in-system, Byte-Programmable EPROM, organized in a contiguous block from
addresses 0x0000 to 0x1FFF. Note that 512 bytes (0x1E00 – 0x1FFF) of this memory are reserved for fac-
tory use and are not available for user program storage. The C8051T602/3 implements 4096 bytes of
EPROM program memory space; the C8051T604/5 implements 2048 bytes of EPROM program memory
space, and the C8051T606 implement 1536 bytes of EPROM program memory space. C2 Register Defini-
tion 15.1 shows the program memory maps for C8051T600/1/2/3/4/5/6 devices.
C8051T600/1
Security Byte
Reserved
0x1FFF
0x1FFE
0x1E00
0x1DFF
7680 Bytes
EPROM Memory
0x0000
C8051T602/3
Security Byte
0x1FFF
0x1FFE
C8051T604/5
Security Byte
0x1FFF
0x1FFE
Reserved
0x1000
0x0FFF
Reserved
4096 Bytes
EPROM Memory
0x0000
2048 Bytes
EPROM Memory
0x0800
0x07FF
0x0000
Figure 15.1. Program Memory Map
C8051T606
0x1FFF
Reserved
Security Byte
1536 Bytes
EPROM Memory
0x07FF
0x0600
0x05FF
0x0000
Program memory is read-only from within firmware. Individual program memory bytes can be read using
the MOVC instruction. This facilitates the use of EPROM space for constant storage.
74
Rev. 1.2
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