C8051T600/1/2/3/4/5/6
Interrupt Source
Table 17.1. Interrupt Summary
Interrupt Priority Pending Flag
Vector Order
Enable
Flag
Priority
Control
Reset
0x0000 Top
External Interrupt 0
(INT0)
Timer 0 Overflow
External Interrupt 1
(INT1)
Timer 1 Overflow
UART0
0x0003 0
0x000B 1
0x0013 2
0x001B 3
0x0023 4
Timer 2 Overflow
0x002B 5
SMB0
0x0033 6
ADC0
0x003B 7
Window Compare
ADC0
0x0043 8
Conversion Complete
Programmable
0x004B 9
Counter Array
Comparator0
0x0053 10
Falling Edge
Comparator0
0x005B 11
Rising Edge
None
IE0 (TCON.1)
N/A N/A Always Always
Enabled Highest
Y Y EX0 (IE.0) PX0 (IP.0)
TF0 (TCON.5)
IE1 (TCON.3)
Y Y ET0 (IE.1) PT0 (IP.1)
Y Y EX1 (IE.2) PX1 (IP.2)
TF1 (TCON.7)
Y Y ET1 (IE.3) PT1 (IP.3)
RI0 (SCON0.0)
Y N ES0 (IE.4) PS0 (IP.4)
TI0 (SCON0.1)
TF2H (TMR2CN.7)
Y N ET2 (IE.5) PT2 (IP.5)
TF2L (TMR2CN.6)
SI (SMB0CN.0)
Y N ESMB0 PSMB0
(EIE1.0) (EIP1.0)
AD0WINT (ADC0CN.3) Y N EWADC0 PWADC0
(EIE1.1) (EIP1.1)
AD0INT (ADC0CN.5) Y N EADC0 PADC0
(EIE1.2) (EIP1.2)
CF (PCA0CN.7)
Y N EPCA0 PPCA0
CCFn (PCA0CN.n)
(EIE1.3) (EIP1.3)
CP0FIF (CPT0CN.4) N N ECP0
PCP0
(EIE1.4) (EIP1.4)
CP0RIF (CPT0CN.5) N N ECP0
PCP0
(EIE1.5) (EIP1.5)
17.2. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described in this section.
Refer to the data sheet section associated with a particular on-chip peripheral for information regarding
valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
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Rev. 1.2