C8051T603 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
'C8051T603' PDF : 168 Pages View PDF
C8051T600/1/2/3/4/5/6
SFR Definition 17.3. EIE1: Extended Interrupt Enable 1
Bit
7
Name
Type
R
Reset
0
6
5
4
3
2
1
0
ECP0R ECP0F EPCA0 EADC0 EWADC0 ESMB0
R
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
SFR Address = 0xE6
Bit Name
Function
7:6 Unused Unused. Read = 00b; Write = Don’t Care.
5 ECP0R Enable Comparator0 (CP0) Rising Edge Interrupt.
This bit sets the masking of the CP0 rising edge interrupt.
0: Disable CP0 rising edge interrupts.
1: Enable interrupt requests generated by the CP0RIF flag.
4 ECP0F Enable Comparator0 (CP0) Falling Edge Interrupt.
This bit sets the masking of the CP0 falling edge interrupt.
0: Disable CP0 falling edge interrupts.
1: Enable interrupt requests generated by the CP0FIF flag.
3 EPCA0 Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
2 EADC0 Enable ADC0 Conversion Complete Interrupt.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
1 EWADC0 Enable Window Comparison ADC0 Interrupt.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT).
0 ESMB0 Enable SMBus (SMB0) Interrupt.
This bit sets the masking of the SMB0 interrupt.
0: Disable all SMB0 interrupts.
1: Enable interrupt requests generated by SMB0.
Rev. 1.2
85
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