Read/Write Cycle Timing (Multiplexed)
t7
nCS
t1
t8
ASTRB
R/nW
t5
t10
DSTRB
AD[8:0]
t2
Address
t9
t3
t4
t6
Data
FIGURE 14 - READ/WRITE CYCLE (MULTIPLEXED ADDRESS AND DATA)
TABLE 40 - READ/WRITE CYCLE TIMING PARAMETERS (MULTIPLEXED ADDRESS AND DATA)
NAME
DESCRIPTION
MIN
TYP MAX UNITS
t1
Address Strobe Setup Time
30
ns
t2
Address Strobe Hold Time
8
15
ns
t3
Data Strobe Pulse Width
85
ns
t4
Data Valid to R/nW Pulse Inactive
30
ns
t5
Chip Select Active to R/nW Pulse Active
15
ns
t6
Data Hold time
5
ns
t7
Address Strobe Inactive to nCS Active
0
5
ns
t8
Address Strobe Pulse Width
23
ns
t9
R/nW Pulse Active to Address Strobe Inactive
15
ns
Note 1
t10
Address Strobe Inactive to R/nW Pulse Active
10
Note 1: Chip select must be latched internally and released when write pulse goes inactive.
43