CC1111F32RSPR View Datasheet(PDF) - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS

Part Name

Description

MFG CO.

CC1111F32RSPR

Low-power sub-1 GHz RF System-on-Chip (SoC) with MCU, memory, transceiver, and USB controller

TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS 

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CC1110Fx / CC1111Fx

IRCON2 (0xE8) – CPU Interrupt Flag 5

Bit Name

Reset R/W Description

7:5

0

R/W Not used

4 WDTIF

0

3 P1IF

0

2 UTX1IF / 0

I2STXIF

1 UTX0IF

0

0 P2IF /

0

USBIF

R/W Watchdog timer interrupt flag

0 Interrupt not pending

1 Interrupt pending

R/W Port 1 interrupt flag.

0 Interrupt not pending

1 Interrupt pending

R/W

USART1 TX interrupt flag / I2S TX interrupt flag

0 Interrupt not pending

1 Interrupt pending

R/W USART0 TX interrupt flag

0 Interrupt not pending

1 Interrupt pending

R/W Port2 interrupt flag / USB interrupt flag

0 Interrupt not pending

1 Interrupt pending

11.5.3 Interrupt Priority

The interrupts are grouped into six interrupt

priority groups and the priority for each group

is set by the registers IP0 and IP1. The

interrupt priority groups with assigned interrupt

sources are shown in Table 42. Each group is

assigned one of four priority levels, and by

default all six interrupt priority groups are

assign the lowest priority. In order to assign a

higher priority to an interrupt, i.e. to its interrupt

group, the corresponding bits in IP0 and IP1

must be set as shown in Table 41 on page 70.

While an interrupt service request is in

progress, it cannot be interrupted by a lower or

same level interrupt. In the case when

interrupt requests of the same priority level are

received simultaneously, the polling sequence

shown in Table 43 is used to resolve the

priority of each requests.

IP1 (0xB9) – Interrupt Priority 1

Bit Name

Reset R/W

7:6

0

R/W

Description

Not used

5 IP1_IPG5 0

4 IP1_IPG4 0

3 IP1_IPG3 0

2 IP1_IPG2 0

1 IP1_IPG1 0

0 IP1_IPG0 0

R/W Interrupt group 5, priority control bit 1, refer to Table 41

R/W Interrupt group 4, priority control bit 1, refer to Table 41

R/W Interrupt group 3, priority control bit 1, refer to Table 41

R/W Interrupt group 2, priority control bit 1, refer to Table 41

R/W Interrupt group 1, priority control bit 1, refer to Table 41

R/W Interrupt group 0, priority control bit 1, refer to Table 41

SWRS033E

Page 69 of 239

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