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CC1111F32RSPR View Datasheet(PDF) - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS

Part Name
Description
MFG CO.
'CC1111F32RSPR' PDF : 240 Pages View PDF
Flash Controller has completed the operation.
The flash erase operation requires that the
instruction that starts the erase i.e. writing to
FCTL.ERASE is followed by a NOP instruction
CC1110Fx / CC1111Fx
as shown in the example code. Omitting the
NOP instruction after the flash erase operation
will lead to undefined behavior.
; Erase page 1 in flash memory
; Assumes 26 MHz system clock is used
;
CLR EA
; Mask interrupts
C1: MOV A,FCTL
; Wait until flash controller is ready
JB
ACC.7,C1
MOV FADDRH,#02h
; Setup flash address (FADDRH[5:1] = 1)
MOV FWT,#2Ah
; Setup flash timing
MOV FCTL,#01h
; Erase page
NOP
; Must always execute a NOP after erase
RET
; Continues here when flash is ready
Figure 24: Flash Page Erase Performed from Flash Memory
13.3.4 Flash DMA trigger
When the DMA channel is armed and the
FLASH trigger selected TRIG[4:0]=10010,
starting a flash write by setting FCTL.WRITE
to 1 will trigger the first DMA transfer. The
following DMA transfers will be triggered by
the Flash Controller when the Flash Write
Data register, FWDATA, is ready to receive new
data.
13.3.5 Flash Write Timing
The Flash Controller contains a timing
generator, which controls the timing sequence
of flash write and erase operations. The timing
generator uses the information set in the Flash
Write Timing register, FWT.FWT[5:0], to set
the internal timing. FWT.FWT[5:0] must be
set to a value according to the currently
selected system clock frequency.
The value used for FWT.FWT[5:0] is given by
the following equation:
21000 F
FWT =
16 *109
where F is the system clock frequency. The
initial value held in FWT.FWT[5:0] after a
reset is 0x11, which corresponds to 13 MHz
system clock frequency (calibrated HS
RCOSC frequency for CC1110Fx when using a
26 MHz XOSC).
13.3.6 Flash Controller Registers
The Flash Controller registers are described in
this section.
SWRS033E
Page 89 of 239
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