CDK8920A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CDK8920A' PDF : 144 Pages View PDF
CS8920A
Bus Interface Register:
DMA Start-of-Frame (Read only)
Address 0027h
Most-significant byte of offset value
Address: PacketPage base + 0026h
Address 0026h
Least-significant byte of offset value
The DMA Start-of-Frame Register contains a 16-bit value which defines the offset from the DMA base address to
the start of the most recently transferred received frame. See Section 5.5.
This register’s initial state after reset is: 0000 0000 0000 0000
Bus Interface Register:
DMA Frame Count (Read only)
Address 0029h
Most-significant byte of frame count
(most-significant nibble always 0h)
Address: PacketPage base + 0028h
Address 0028h
Least-significant byte of frame count
The lower 12 bits of the DMA Frame Count register define the number of valid frames transferred via DMA since
the last readout of this register. The upper 4 bits are reserved. See Section 5.5.
This register’s initial state after reset is: XXXX 0000 0000 0000
Bus Interface Register:
RxDMA Byte Count (Read only)
Address 002Bh
Most-significant byte of byte count.
Address: PacketPage base + 002Ah
Address 002Ah
Least-significant byte of byte count.
The RxDMA Byte Count register describes the valid number of bytes DMAed since the last readout. See Section
5.5.
This register’s initial state after reset is: 0000 0000 0000 0000
DS238PP2
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