CDK8920A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CDK8920A' PDF : 144 Pages View PDF
counters. The Event registers are RxEvent (Reg-
ister 4), TxEvent (Register 8), and BufEvent
(Register C). The counters are RxMISS (Register
10) and TxCOL (Register 12). Each Interrupt
Enable bit and its associated Event are identified
in Table 4.3.
An Event bit is set whenever the specified event
happens, whether or not the associated Interrupt
Enable bit is set. All Event registers are cleared
upon readout by the host.
Accept Bits
There are nine Accept bits located in the RxCTL
register (Register 5), each of which is followed
by the suffix A. Accept bits indicate which types
Interrupt Enable Bit
(register name)
Event Bit or Counter
(register name)
ExtradataiE (RxCFG)
RuntiE (RxCFG)
CRCerroriE (RxCFG)
RxOKiE (RxCFG)
Extradata (RxEvent)
Runt (RxEvent)
CRCerror (RxEvent)
RxOK (RxEvent)
16colliE (TxCFG)
AnycolliE (TxCFG)
JabberiE (TxCFG)
Out-of-windowiE (TxCFG)
TxOKiE (TxCFG)
SQEerroriE (TxCFG)
Loss-of-CRSiE (TxCFG)
16coll (TxEvent)
"Number-of-Tx-collisions"
counter is incremented
(TxEvent)
Jabber (TxEvent)
Out-of-window (TxEvent)
TxOK (TxEvent)
SQEerror (TxEvent)
Loss-of-CRS (TxEvent)
MissOvfloiE (BufCFG)
TxColOvfloiE (BufCFG)
RxDestiE (BufCFG)
Rx128iE (BufCFG)
RxMissiE (BufCFG)
TxUnderruniE (BufCFG)
Rdy4TxiE (BufCFG)
RxDMAiE (BufCFG)
RxMISS counter overflows
past 1FFh
TxCOL counter overflows
past 1FFh
RxDest (BufEvent)
Rx128 (BufEvent)
RxMISS (BufEvent)
TxUnderrun (BufEvent)
Rdy4Tx (BufEvent)
RxDMAFrame (BufEvent)
Table 4.3. Interrupt Enable Bits and Events
CS8920A
of frames will be accepted by the CS8920A. (A
frame is said to be "accepted" by the CS8920A
when the frame data are placed in either on-chip
memory, or in host memory by DMA.) Four of
these bits have corresponding Interrupt Enable
(iE) bits. An Accept bit and an Interrupt Enable
bit are independent operations. It is possible to
set either, neither, or both bits. The four corre-
sponding pairs of bits are:
iE Bit in RxCFG
ExtradataiE
RuntiE
CRCerroriE
RxOKiE
A Bit in RxCTL
ExtradataA
RuntA
CRCerrorA
RxOKA
If one of the above Interrupt Enable bits is set
and the corresponding Accept bit is clear, the
CS8920A generates an interrupt when the associ-
ated receive event occurs, but then does not
accept the receive frame (the length of the re-
ceive frame is set to zero).
The other five Accept bits in RxCTL are used for
destination address filtering (see Section 5.3).
The Accept mechanism is explained in more de-
tail in Section 5.2.
4.4.2 Status and Control Register Summary
The figure on the following page (Figure 4.2)
provides a summary of the Status and Control
registers. Section 4.4.2 gives a detailed descrip-
tion of each Status and Control register.
DS238PP2
47
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