CHA3093C View Datasheet(PDF) - United Monolithic Semiconductors
Part Name
Description
MFG CO.
'CHA3093C' PDF : 10 Pages View PDF
CHA3093c
20-40GHz Medium Power Amplifier
Typical Bias Tuning
The circuit schematic is given below:
Vd1
IN
Vd 2,3,4
OUT
Vg1
Vg 2
Vg 3,4
Vdet
For medium power operation, the four drain biases are connected altogether. In a same way,
all the gate biases are connected together at the same power supply, tuned to drive a small
signal operating current of 300mA. A separate access to the gate voltages of the two first
stages (Vg1, 2) is provided in order to be able to tune the first stages for the application, as a
lower noise amplifier or a multiplier.
An additional pad is provided for monitoring the output power, using the Build In Test. This
access, when connected to an external resistor of 10Kohm (typical value) provides a DC
voltage which follows the output power level.
On wafer power measurements versus output power
Ref. : DSCHA30932158 -07-June-02
8/10
Specifications subject to change without notice
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