CL-PD6833-QC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-QC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
5.3 Revision ID and Class Code
Byte 3
Class Code
(high)
Byte 2
Class Code
(mid.)
Byte 1
Class Code
(low)
Register Name: Revision ID and Class Code
Offset: 08h
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Class Code (high)
Bit 23
Bit 22
Bit 21
R:00000110
Bit 20
Bit 19
Bit 15
Bit 14
Bit 13
Class Code (mid.)
R:00000111
Bit 12
Bit 11
Bit 7
Bit 6
Bit 5
Class Code (low)
R:00000000
Bit 4
Bit 3
Bit 26
Bit 18
Bit 10
Bit 2
Byte 0
1
1
Revision ID
R:1
R:1
a This read-only value depends on the revision level of the CL-PD6833.
Revision ID
R:nnnnnna
Register Per: socket
Bit 25
Bit 24
Bit 17
Bit 16
Bit 9
Bit 8
Bit 1
Bit 0
Bits 7:0 — Revision ID (‘11100001’)
This read-only field identifies the revision level of the CL-PD6833. It reflects the value of bits 5:0
of the Chip Information register (index 1Fh). Bits 7 and 6 always read back a ‘1’.
NOTE: Having bits 4:0 as ‘0’ indicates that the Device ID registers described in Section 11.9 on page 159 should
be used in determining Revision ID.
Bits 31:8 — Class Code
This field always reads back 060700h, identifying the CL-PD6833 as a PCMCIA/CardBus bridge
device.
52
PCI CONFIGURATION REGISTERS
ADVANCE DATA BOOK v0.3
June 1998
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