CL-PD6833-QC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-QC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
5.5 Memory Base Address
Register Name: Memory Base Address
Offset: 10h
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Register Per: socket
Bit 25
Bit 24
Byte 3
Bit 23
Bit 22
Controller Memory Base Address (high)
Bit 21
R/W:00000000
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Byte 2
Controller Memory Base Address (high mid.)
R/W:00000000
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Byte 1
Controller Memory Base Address (low mid.)
Controller Memory Base Address (low mid.)
Byte 0
R/W:0000
Bit 7
Bit 6
Bit 5
Bit 4
Controller Memory Base Address (low)
R:0000
Bit 3
Prefetchable
R:0
R:0000
Bit 2
Bit 1
Type
R:00
Bit 0
Memory
Space
Indicator
R:0
This is the PCI memory address space base address for the Operation registers.
Bit 0 — Memory Space Indicator
This bit always reads back ‘0’, indicating that this base address register defines a PCI memory
space.
Bits 2:1 — Type
These bits indicate that the controller can be located anywhere in the 32-bit address space.
Bit 3 — Prefetchable
This bit indicates that the Controller registers are not prefetchable.
Bits 31:4 — Controller Memory Base Address
This field specifies the memory-mapped register space of the CL-PD6833. The Operation
registers can be accessed through this window only after these bits are set to a non-zero value.
54
PCI CONFIGURATION REGISTERS
ADVANCE DATA BOOK v0.3
June 1998
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