CL-PD6833-QC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-QC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
6. CARDBUS REGISTERS
The CardBus registers occupy offsets 000h–7FFh from the Memory Base Address register. These
registers are reset by RST#.
Table 6-1. CardBus Registers Quick Reference
Register Name
Status Event — PME_CXT
Status Mask — PME_CXT
Present State
Event Force
Control — PME_CXT
Memory Offset
000h
004h
008h
00Ch
010h
Page Number
75
77
78
80
82
6.1 Status Event — PME_CXT
Register Name: Status Event — PME_CXT
Memory Offset: 000h
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Byte 3
Reserved
Bit 23
Bit 22
Bit 21
R:00000000
Bit 20
Bit 19
Bit 18
Byte 2
Reserved
Bit 15
Bit 14
Bit 13
R:00000000
Bit 12
Bit 11
Bit 10
Byte 1
Reserved
R:00000000
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Byte 0
Reserved
Power Cycle CCD2
R:0000
R/C:0
R/C:0
Register Per: socket
Bit 25
Bit 24
Bit 17
Bit 16
Bit 9
Bit 8
Bit 1
CCD1
R/C:0
Bit 0
CSTSCHG/
WAKEUP
R/C:0
NOTE: PME_CXT (PME Context) is a set of register bits that do not get reset or initialized if PME Enable is true
when the CL-PD6833 changes power states from D3 to D0 through a software PCI Bus Segment reset.
The Status Event register indicates when a change in socket status occurs. These bits do not indicate
what the change is, only that a change occurred. Software must read the Present State register for cur-
rent status. Bits 3:0 can be cleared by writing a ‘1’ to each bit. These bits can be set to ‘1’ by software
through writing ‘1’ to the corresponding bit in the Event Force register, provided the Status Mask register
has been set. All bits in this register are cleared by RST#. Software needs to clear this register before
enabling interrupts.
June 1998
ADVANCE DATA BOOK v0.3
75
CARDBUS REGISTERS
Share Link: 
