CL-PD6833-QC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-QC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
6.2 Status Mask — PME_CXT
Register Name: Status Mask — PME_CXT
Memory Offset: 004h
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Byte 3
Reserved
Bit 23
Bit 22
Bit 21
R:00000000
Bit 20
Bit 19
Byte 2
Reserved
Bit 15
Bit 14
Bit 13
R:00000000
Bit 12
Bit 11
Byte 1
Reserved
Bit 7
Byte 0
Bit 6
Bit 5
Reserved
R:0000
R:00000000
Bit 4
Bit 3
Power
Cycle
Complete
R/W:0
Bit 26
Bit 18
Bit 10
Bit 2
CCD2
Changed
R/W:0
Register Per: socket
Bit 25
Bit 24
Bit 17
Bit 16
Bit 9
Bit 8
Bit 1
CCD1
Changed
R/W:0
Bit 0
CSTSCHG/
WAKEUP
R/W:0
NOTE: PME_CXT (PME Context) is a set of register bits that do not get reset or initialized if PME Enable is true
when the CL-PD6833 changes power states from D3 to D0 by a software PCI Bus Segment reset.
This register gives software the ability to control the events that can cause interrupts. If the Card Detect
Changed bit is enabled at the time a card is removed, an interrupt is generated. This register is cleared
automatically when card is removed. If the CL-PD6833 is required to generate an interrupt when a new
card is inserted, software must again set the Card Detect Changed mask bit.
Bit 0 — CSTSCHG/WAKEUP (Card Status Change / Wakeup)
When set, this bit enables an interrupt based on the CSTSCHG signal being asserted by a
CardBus card. CSTSCHG interrupts generated by 16-bit cards are controlled by registers in that
interface’s register space. This bit is disabled when it is ‘0’.
Bit 1 — CCD1 Changed
When set, this bit enables an interrupt when the CL-PD6833 detects change.
Bit 2 — CCD2 Changed
When set, this bit enables an interrupt when the CL-PD6833 detects change.
Bit 3— Power Cycle Complete
When set, this bit causes the CL-PD6833 to generate an interrupt 256 cycles of the PCI clock after
powering up a socket.
Bits 31:4 — Reserved
June 1998
ADVANCE DATA BOOK v0.3
77
CARDBUS REGISTERS
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