CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
13.3 Mid High Address
Register Name: Mid High Address
I/O Index: 2h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Mid High Address
8 bit 23:16
16 bit 23:17
R/W:00000000
Register Per: socket
Register Compatibility Type: DMA
Bit 2
Bit 1
Bit 0
This register is used to form part of the address for DMA transfers.
Bits 7:0 — Mid High Address
This register corresponds to the Base and Current Address register of the Intel 8237 for write operations.
For read operations this register contains the Current Address. When bits 2:1 of the DMA Slave
Configuration register indicate that an 8-bit transfer is to occur, this register contains the starting
address bits 23:16. If bits 2:1 of the DMA Slave Configuration register indicate that a 16-bit
transfer is to occur, then this register contains low address bits 23:17, and bit 0 of this register is
not used.
13.4 High Address
Register Name: High Address
I/O Index: 3h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
High Address
8 bit 31:24
16 bit 31:24
R/W:00000000
Register Per: socket
Register Compatibility Type: DMA
Bit 2
Bit 1
Bit 0
This register is used to form part of the address for DMA transfers. This register is only employed to
indicate the memory address of the DMA transfer when bit 3 of the DMA Slave Configuration is set to a
‘1’.
Bits 7:0 — High Address
This register corresponds to the Base and Current Address register of the Intel 8237 for write
operations. For read operations this register contains the current address. This register contains
the starting address bits 31:24. This register is enabled by bit 3 of the DMA Slave Configuration
register. If bit 3 of the DMA Slave Configuration is reset, then address bits 31:24 are ‘00’ during
DMA transfers from the CL-PD6833 to memory.
June 1998
ADVANCE DATA BOOK v0.3
DMA OPERATION REGISTERS
173
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