CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
5.2 Command and Status
Byte 3
Status
(high)
Byte 2
Status
(low)
Byte 1
Command
(high)
Byte 0
Command
(low)
Register Name: Command and Status
Offset: 04h
Bit 31
Bit 30
Bit 29
Bit 28
Address/Data System Error
Parity Error (SERR#)
Detected
Generated
RC:0
RC:0
Bit 23
Bit 22
Received
Master Abort
RC:0
Bit 21
Received
Target Abort
RC:0
Bit 20
Fast Back-to-
UDF
Back Capable Supported
R:0
Bit 15
R:0
Bit 14
66-MHz
Supported
R:0
Bit 13
New
Capabilities
Present
R:1
Bit 12
Bit 27
Signalled
Target Abort
RC:0
Bit 19
Bit 11
Reserved
Bit 7
Wait Cycle
Control
R:0
Bit 6
Parity Error
Check/Report
Enable
R/W:0
Bit 5
Reserved
R:0
R:0000000
Bit 4
Bit 3
Memory Write
and Invalidate
Enable
Special Cycle
Enable
R:0
R:0
Register Per: socket
Bit 26
Bit 25
DEVSEL# Timing
R:01
Bit 18
Bit 17
Bit 24
Master Data
Parity Error
Reported
RC:0
Bit 16
Reserved
R:0000
Bit 10
Bit 9
Bit 2
Bit 1
Bit 8
System Error
(SERR#)
Enable
R/W:0
Bit 0
Bus Master PCI Memory
PCI I/O
Enable Space Enable Space Enable
R/W:0
R/W:0
R/W:0
Bit 0 — PCI I/O Space Enable
This bit does not affect R2 I/O space.
If this bit is ‘0’ for both Sockets A and B, any reads or writes to the I/O registers of the CL-PD6833 are
0
ignored. If this bit is a ‘1’, I/O accesses to the registers or CardBus card are carried out. For
configuration space 0, I/O accesses to both sockets are disabled.
The I/O space for the CL-PD6833 is enabled and responds to the reads and writes to the I/O address
1
range defined in I/O Base Address register as well as any I/O window addresses. For configuration
space 0, this bit enables I/O register accesses for both Sockets A and B.
Bit 1 — PCI Memory Space Enable
This bit must be set for the CL-PD6833 to respond to memory transactions. This bit does not affect
R2 memory space.
0
The memory space for the CL-PD6833 is disabled. Any reads or writes to the CL-PD6833 memory
space are ignored.
1
The memory space for the CL-PD6833 is enabled, allowing access to memory window and memory-
mapped CL-PD6833 registers.
Bit 2 — Bus Master Enable
This bit must be set to enable the bus master capability in the CL-PD6833.
0
Bus master capability disabled.
1
Bus master capability enabled.
June 1998
ADVANCE DATA BOOK v0.3
49
PCI CONFIGURATION REGISTERS
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