CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
Bit 28 — Received Target Abort
To clear this bit, software must write a ‘1’ to it.
0
No master transaction has been terminated with a target abort.
1
A master transaction has been terminated with a target abort.
Bit 29 — Received Master Abort
To clear this bit, software must write a ‘1’ to it.
0
No transaction has been terminated due to master abort.
1
A master device has terminated its transaction with master abort.
Bit 30 — System Error (SERR#) Generated
This bit is set whenever the CL-PD6833 asserts SERR# because of internal detection of a PCI
address parity error. Bit 8 of this register must be set before system errors can be reported, and
bit 6 must be set to allow address parity errors to be detected. The CL-PD6833 only asserts
SERR# if address parity errors occur. To clear this bit, software must write a ‘1’ to it.
0
SERR# was not asserted by this device.
1
SERR# was asserted by this device, indicating a PCI address parity error.
Bit 31 — Address/Data Parity Error Detected
This bit indicates whether a parity error was detected, independent of whether bit 6 of this register
is ‘1’. To clear this bit, software must write a ‘1’ to it.
0
No data parity errors detected.
1
Address or data parity error detected.
June 1998
ADVANCE DATA BOOK v0.3
51
PCI CONFIGURATION REGISTERS
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