CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
5.9 Memory Limit 0–1
Register Name: Memory Limit 0–1
Offset: 20h, 28h
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Register Per: socket
Bit 25
Bit 24
Byte 3
Memory Limit 31:24
Byte 2
Bit 23
Bit 22
Bit 21
R/W:00000000
Bit 20
Bit 19
Memory Limit 23:16
Bit 18
Bit 17
Bit 16
Byte 1
Bit 15
Bit 14
Bit 13
Memory Limit 15:12
R/W:00000000
Bit 12
Bit 11
Bit 10
Bit 9
Memory Limit 11:8
Bit 8
Bit 7
Byte 0
R/W:0000
Bit 6
Bit 5
Bit 4
Bit 3
Memory Limit 7:0
R:0000
Bit 2
Bit 1
Bit 0
R:00000000
NOTE: Memory Base 0–1 and Memory Limit 0–1 are enabled by bit 1 of the Command and Status register
(memory offset 04h). To disable one window, set bits 31:12 to the limit of that window equal to or below the
corresponding base address.
Bits 31:0 — Memory Limit 31:0
This register defines the top address of a PCI memory window to be mapped to CardBus-capable
PC Card memory space. The upper 20 bits correspond to PCI address bits AD[31:12]. The bottom
12 bits (which correspond to PCI address bits AD[11:0]) are read-only and return ‘0’ when read;
however, the bridge assumes PCI address bits AD[11:0] are ‘1’s to determine the range defined,
so if Memory Base 0–1 and Memory Limit 0–1 registers are set to the same value, a 4-Kbyte
window is defined.
June 1998
ADVANCE DATA BOOK v0.3
59
PCI CONFIGURATION REGISTERS
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