CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
5.4 Cache Line Size, Latency Timer, Header Type, and BIST
Register Name: Cache Line Size, Latency Timer, Header Type, and BIST
Offset: 0Ch
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Byte 3
BIST
Bit 23
Bit 22
Bit 21
BIST
R:00000000
Bit 20
Bit 19
Bit 18
Byte 2
Header Type
Byte 1
Latency
Timer
Byte 0
Cache Line
Size
Bit 15
Bit 7
Bit 14
Bit 13
Header Type
R:10000010
Bit 12
Bit 11
Latency Timer 7:3
R/W:00000
Bit 6
Bit 5
Bit 4
Bit 3
Cache Line Size
R:00000000
Bit 10
Bit 2
Register Per: socket
Bit 25
Bit 24
Bit 17
Bit 16
Bit 9
Bit 8
Latency Timer 2:0
R:000
Bit 1
Bit 0
Bits 7:0 — Cache Line Size
This read-only field is always 00h, indicating that the CL-PD6833 does not participate in PCI-
defined caching algorithms, and only generates memory write invalidate as a result of a PC Card
32 master cycle.
Bits 15:8 — Latency Timer 7:0
This field programs the master latency time-out value. If the full byte is available, the latency timer
programs in increments of one PCI clock (PCI_CLK), but because bits 10:8 on the CL-PD6833 are
read-only and must be programmed to 0h, master latency time-out values are programmable in
increments of eight PCI clocks.
Bits 23:16 — Header Type
This read-only field is always 82h, specifying that the CL-PD6833 is a multi-function PCI-to-
CardBus bridge.
Bits 31:24 — BIST
This read-only field is reserved for BIST information. If this field returns all ‘0’s on a read, then this
device does not contain a BIST.
June 1998
ADVANCE DATA BOOK v0.3
53
PCI CONFIGURATION REGISTERS
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