CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
Bit 29 — Received Master Abort
To clear this bit, software must write a ‘1’ to it.
0
No transaction has been terminated due to master abort.
1
A master device has terminated its transaction with master abort.
Bit 30 — Received System Error (SERR#)
This bit is set whenever the CardBus interface detects an address parity error. Bit 17 of the
Interrupt Line, Interrupt Pin, and Bridge Control register (memory offset 3Ch) must be set
before system errors can be reported, and bit 16 of the Interrupt Line, Interrupt Pin, and Bridge
Control register must be set to allow address parity errors to be detected. The CL-PD6833 only
asserts SERR# if address parity errors occur. To clear this bit, software must write a ‘1’ to it.
0
SERR# assertion on the CardBus interface has not been detected.
1
SERR# assertion on the CardBus interface has been detected.
Bit 31 — Address/Data Parity Error Detected
This bit indicates whether a parity error was detected, independent of whether bit 16 of the Bridge
Control register (memory offset 3Ch) is ‘1’. To clear this bit, software must write a ‘1’ to it.
0
No data parity errors detected.
1
Address or data parity error detected.
56
PCI CONFIGURATION REGISTERS
ADVANCE DATA BOOK v0.3
June 1998
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